TB711FC1
TB711FC1
TB711FC1
TB711FC1
TB711FC1
ABB 原产地：瑞士
主营旗下三大系列：
1. ABB DCS过程控制系统
①ABB FreeLance AC800F电源模件：
SA801F/SA811F/SD802F/SD812F
PM802F/PM803F
FI810F/FI820F/FI830F/FI840F
EI811F/ABB EI812F/ABB EI813F
07KT97B/ 07AC91D
②ABB S800 IO模拟量I/O模件
AI801/ AI810/ AI825/ AO801/ AO845/ AO895
③ABB S800 IO开关量I/O模件
DI801/ DI810/ DO801/ DO810④ABB张力计
PFEA111／PFEA112
2. ABB Bailey 贝利
第一代（80年）DCS系统：Network-90
第一代（80年）DCS系统：Network-90
主营：第三代（94年）DCS系统：Infi-90 Open
IMASI23/IMHSS03/IMDS../INICI../IMRD../IE../BRC…
第四代（98年）DCS系统：Symphony
主营：第五代 最新DCS系统：
SPBRC300/SPBRC400/SPNIS21/SPNPM22
3. ABB 机器人系统
常用配件系列：DSQC…/3HAB…/3HAC…./3HAA…/3HNE….
高压变频系列：5SD……./5SHX…./5SHY……
87TS01I-E GJR2368900R2342
87TS01I-E GJR2368900R2551
89NU01E 89NU01C-E GJR2329100R0100
L0055958 07KT98 GJR5253100R3260
83sr09e 83sr09d-e gjr2366500r1010
83sr05g-e gjr2369900r1100
81AA01E 81AA01L-E GJR2370100R1000
88QT03E 88QT03A-E GJR2374500R2011
87TS01K-E GJR2368900R1313
GJR2263300R10 VT372CR10
gjr2265100r10 VT373Cr10
88tk02a-e gjr2370400r1040
88TK02A-E GJR2370400R1040
35am50 gjr5-1391-11p6
88VP02B-E GJR2371100R1040
88QT02C-E GJR2342500R1000
11UX16C-E GJR2373300R0001
81AA10I-E GJR2370200R1100
81AA10I-E GJR2370200R1100
81AA10I-E GJR2370200R1100
81AA10I-E GJR2370200R1100
88fn02a-e gjr2370800r0200
88FN02A-E GJR2370800R0200
81AA01E GJR2370100R1000
81ea11d-e gjr2374800r0210
81EA11D-E GJR2374800R0210
88fn02b-e gjr2370800r0200
88FN02B-E GJR2370800R0200
81EA02E-E GJR2366000R1000
81EA02E-E GJR2366000R1000
81EB02E-E GJR2349000R1000
88TV01L-E GJR2385100R1040
Mb86s02 video image sensor collects video image information under the control of FPGA. After receiving the command of PC, MB86S02 begins to collect video signal. FPGA, as the core control unit of the system, is not only responsible for collecting video image, and is responsible for the video image information pretreatment and the system unit module between the data interaction. In order to ensure the real-time requirement of the system, the system uses a large capacity off-chip Sdramr to cache the video image information, and the SDRAM controller is implemented by FPGA, after the video image information is buffered by SDRAM, it is first filtered by FPGA to eliminate the noise interference in the image information. In this system, the video information is processed by means of median filter, after filtering the data into the DSP through the FPGA internal Fifo next step compression processing. After power-on, the DSP first loads the bootstrap program and waits for the FPGA to send the request. After receiving the FPGA request, the DSP establishes the Edma Channel to obtain the video data from the FPGA, after storing a full frame, the DSP begins to compress the video image with Jpeg, after the compressed video image information is stored in Fifo, it is written into the USB interface controller's data buffer under the control of FPGA, waiting for the PC's reading request, the USB interface controller writes the data to Port 1 of PDIUSBD12 after receiving the reading request from the PC, so that the PC can read the data next. 2 system software overall design, system software design according to the overall division of hardware structure, can also be divided into two major parts to describe. The whole system runs as shown in figure 2, FPGA AND DSP program run independently, through interrupt signal to complete the real-time interaction of data. The instruction of FPGA TO DSP is to send an Edma request through FPGA. DSP responds the Edma Request, establishes the Edma Channel, and begins to read the pre-processed data from FIFO. When DSP transmits the data to FPGA, it sends an interrupt signal to FPGA, let it read out the compressed image data from Fifo. The whole work flow of the system can be described as follows: After the system is powered on, the DSP is first bootstrapped by Flash, and the BOOTSTRAP program is run, then it is put into the Edma waiting state, and the FPGA initializes and waits for the external image acquisition command, after receiving the command of image collection, the image is collected and preprocessed. The preprocessed image is buffered. After storing a certain amount of data, the FPGA sends the EDMA REQUEST TO DSP through half full signal, once the DSP receives the Edma request from FPGA, it immediately establishes the Edma Channel, reads the data from Fifo to l2 memory, after storing a frame of image, the DSP starts the image compression, after waiting for an image compression to complete, dSP will send an interrupt signal to FPGA, FPGA receives the interrupt signal and begins to read the compressed image data from Fifo. After reading a frame of data, to determine whether the encoding signal is valid, if valid then according to the same rules for the next frame of image compression, if invalid then inform the DSP end. 3 conclusion, the design scheme has been verified by hardware, achieved the design requirements and realized the real-time processing of large amount of data. The system volume is only 7070mm, power consumption is less than 5W, median filtering rate is 20F / S, JPEG compression rate is above 25F / S. It not only meets the real-time requirement of the video processing system, but also has small volume and low power consumption. Moreover, the system has good flexibility and expansibility based on FPGA.
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