A2H124-24FX
A2H124-24FX
A2H124-24FX
联系人：刘锦玲
手 机：15359273791（微信同号）
Email: sales5@xrjdcs,com
地址:福建省厦门市翔安区中国.梦谷1号楼1403
凯创网络公司（Enterasys Networks）是一家美国网络公司，总部位于新罕布什尔州塞勒姆。公司产品主要是联网设备，包括：路由器，交换机，IEEE 802.11无线接入点和控制器。公司于2000年3月从凯创系统公司分拆出来而成立。
除了网络硬件，凯创网络还销售用于管理和保护网络的软件，如入侵防御系统，网络接入控制和安全信息管理。
Enterasys XSR-1805
Enterasys XSR-1850
Enterasys XSR-3020
Enterasys XSR-3250
Enterasys XSR-3020
Enterasys XSR-3150
Enterasys XSR-3250
Enterasys A2系列:
Enterasys A2H124-24
Enterasys A2H124-48
Enterasys A2H124-24FX
Enterasys A2H124-24P
Enterasys A2H124-48P
Enterasys A4H124-24FX
Enterasys B2系列:
Enterasys B2G124-24
Enterasys B2G124-48
Enterasys B2H124-48
Enterasys B2H124-48P
Enterasys B2G124-48P
Enterasys
Enterasys B3系列:
Enterasys
Enterasys B3G124-24
Enterasys B3G124-24P
Enterasys B3G124-48
Enterasys B3G124-48P
Enterasys C2系列:
Enterasys C2G124-48
Enterasys C2G124-24
Enterasys C2G124-48P
Enterasys C2K122-24
Enterasys C2H124-48
Enterasys C2H124-48P
Enterasys C2G134-24P
Enterasys C2G170-24
Enterasys C2L3-LIC
Enterasys C2RPS-PSM
Enterasys C2RPS-CHAS8
Enterasys C2RPS-POE
Enterasys C2RPS-CHAS2
Enterasys C3系列:
Enterasys C3G124-48
Enterasys C3G124-24
Enterasys C3G124-48P
Enterasys C3G124-24P
Enterasys C3L3-LIC
Enterasys C3IPv6-LIC
Enterasys D2系列:
Enterasys D2G124-12
Enterasys D2G124-12P
Enterasys D2G124-12-SYS
Enterasys D2G124-12P-SYS
Enterasys D2POL-LIC
Enterasys D2POL-LIC25
Enterasys D2POL-LIC50
Enterasys D2-PWR
Enterasys D2-PWR-POE
Enterasys D2-LOCKBOX
Enterasys D2-RMT
Enterasys D2-TBL-MNT
Enterasys D2-WALL-MNT
Enterasys I系列工业交换机:
Enterasys I3H252-12TX
Enterasys I3H252-4FXM
Enterasys I3H252-8FXM
Enterasys I3H252-8TX-2FX
Enterasys I3H252-6TX-MEM
Enterasys I3H252-4FX-MEM
Enterasys I3H-12TX
Enterasys I3H-4FX-MM
Enterasys I3H-8FX-MM
Enterasys I3H-6TX-MEM
Enterasys I3H-4FXM-MEM
Enterasys I3H-MEM
Enterasys I3H-PWR
Enterasys I-MGBIC-GZX
Enterasys I-MGBIC-GSX
Enterasys 13H-DIN-KIT
Enterasys I3H-RACK-MNT
Enterasys K系列:
Enterasys K6-Chassis
Enterasys K6-FAN
Enterasys K6-MID-KIT
Enterasys K10-Chassis
Enterasys K10-FAN
Enterasys K10-MID-KIT
Enterasys K-AC-PS-1400W
Enterasys K-POE-4BAY
Enterasys K-POE-4BAY-RAIL
Enterasys KK2008-0204-F2
Enterasys KK2008-0204-F1
Enterasys KT2006-0224
Enterasys KG2001-0224
Enterasys KK2008-0204
Enterasys K-EOS-L3
Enterasys K-EOS-PPC
Enterasys S系列:
Enterasys S8-Chassis
Enterasys S8-Chassis-POE4
Enterasys S8-Chassis-POE8
Enterasys S4-Chassis
Enterasys S4-Chassis-POE4
Enterasys S3-Chassis
Enterasys S3-Chassis-POE4
Enterasys S-AC-PS
Enterasys S-POE-PS
Enterasys S-AC
Enterasys ST4006-0272
Enterasys ST4106-0248
Enterasys SG4101-0248
Enterasys ST4106-0348-F6
Enterasys ST1206-0848-F6
Enterasys SG1201-0848-F6
Enterasys SK1208-0808-F6
Enterasys ST1206-0848
Enterasys SG1201-0848
Enterasys SK1008-0816
Enterasys SOK1208-0102
Enterasys SOK1208-0104
Enterasys SOK1208-0204
Enterasys SOG1201-0112
Enterasys SOT1206-0112
Enterasys SSA-T4068-0252
Enterasys SSA-T1068-0652
Enterasys SSA-G1018-0652
Enterasys SSA-AC-PS-600W
Enterasys SSA-AC-PS-1000W
Enterasys SSA-FAN-KIT
The software design of the system can be divided into two parts according to the General Division of hardware structure. The whole system runs as shown in figure 2, FPGA AND DSP program run independently, through interrupt signal to complete the real-time interaction of data. The instruction of FPGA TO DSP is to send an Edma request through FPGA. DSP responds the Edma Request, establishes the Edma Channel, and begins to read the pre-processed data from FIFO. When DSP transmits the data to FPGA, it sends an interrupt signal to FPGA, let it read out the compressed image data from Fifo. Mb86s02 video image sensor collects video image information under the control of FPGA. After receiving the command of PC, MB86S02 begins to collect video signal. FPGA, as the core control unit of the system, is not only responsible for collecting video image, and is responsible for the video image information pretreatment and the system unit module between the data interaction. In order to ensure the real-time requirement of the system, the system uses a large capacity off-chip Sdramr to cache the video image information, and the SDRAM controller is implemented by FPGA, after the video image information is buffered by SDRAM, it is first filtered by FPGA to eliminate the noise interference in the image information. In this system, the video information is processed by means of median filter, after filtering the data into the DSP through the FPGA internal Fifo next step compression processing. After power-on, the DSP first loads the bootstrap program and waits for the FPGA to send the request. After receiving the FPGA request, the DSP establishes the Edma Channel to obtain the video data from the FPGA, after storing a full frame, the DSP begins to compress the video image with Jpeg, after the compressed video image information is stored in Fifo, it is written into the USB interface controller's data buffer under the control of FPGA, waiting for the PC's reading request, the USB interface controller writes the data to Port 1 of PDIUSBD12 after receiving the reading request from the PC, so that the PC can read the data next. The whole work flow of the system can be described as follows: After the system is powered on, the DSP is first bootstrapped by Flash, and the BOOTSTRAP program is run, then it is put into the Edma waiting state, and the FPGA initializes and waits for the External Image Acquisition Command, after receiving the command of image collection, the image is collected and preprocessed. The preprocessed image is buffered. After storing a certain amount of data, the FPGA sends the EDMA REQUEST TO DSP through half full signal, once the DSP receives the Edma Request from FPGA, it immediately establishes the Edma Channel, reads the data from Fifo to l2 memory, after storing a frame of image, the DSP starts the image compression, after waiting for an image compression to complete, dSP will send an interrupt signal to FPGA, FPGA receives the interrupt signal and begins to read the compressed image data from Fifo. After reading a frame of data, to determine whether the encoding signal is valid, if valid then according to the same rules for the next frame of image compression, if invalid then inform the DSP end.
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