C2G124-24
C2G124-24
C2G124-24
联系人：刘锦玲
手 机：15359273791（微信同号）
Email: sales5@xrjdcs,com
地址:福建省厦门市翔安区中国.梦谷1号楼1403
凯创网络公司（Enterasys Networks）是一家美国网络公司，总部位于新罕布什尔州塞勒姆。公司产品主要是联网设备，包括：路由器，交换机，IEEE 802.11无线接入点和控制器。公司于2000年3月从凯创系统公司分拆出来而成立。
除了网络硬件，凯创网络还销售用于管理和保护网络的软件，如入侵防御系统，网络接入控制和安全信息管理。
Enterasys XSR-1805
Enterasys XSR-1850
Enterasys XSR-3020
Enterasys XSR-3250
Enterasys XSR-3020
Enterasys XSR-3150
Enterasys XSR-3250
Enterasys A2系列:
Enterasys A2H124-24
Enterasys A2H124-48
Enterasys A2H124-24FX
Enterasys A2H124-24P
Enterasys A2H124-48P
Enterasys A4H124-24FX
Enterasys B2系列:
Enterasys B2G124-24
Enterasys B2G124-48
Enterasys B2H124-48
Enterasys B2H124-48P
Enterasys B2G124-48P
Enterasys
Enterasys B3系列:
Enterasys
Enterasys B3G124-24
Enterasys B3G124-24P
Enterasys B3G124-48
Enterasys B3G124-48P
Enterasys C2系列:
Enterasys C2G124-48
Enterasys C2G124-24
Enterasys C2G124-48P
Enterasys C2K122-24
Enterasys C2H124-48
Enterasys C2H124-48P
Enterasys C2G134-24P
Enterasys C2G170-24
Enterasys C2L3-LIC
Enterasys C2RPS-PSM
Enterasys C2RPS-CHAS8
Enterasys C2RPS-POE
Enterasys C2RPS-CHAS2
Enterasys C3系列:
Enterasys C3G124-48
Enterasys C3G124-24
Enterasys C3G124-48P
Enterasys C3G124-24P
Enterasys C3L3-LIC
Enterasys C3IPv6-LIC
Enterasys D2系列:
Enterasys D2G124-12
Enterasys D2G124-12P
Enterasys D2G124-12-SYS
Enterasys D2G124-12P-SYS
Enterasys D2POL-LIC
Enterasys D2POL-LIC25
Enterasys D2POL-LIC50
Enterasys D2-PWR
Enterasys D2-PWR-POE
Enterasys D2-LOCKBOX
Enterasys D2-RMT
Enterasys D2-TBL-MNT
Enterasys D2-WALL-MNT
Enterasys I系列工业交换机:
Enterasys I3H252-12TX
Enterasys I3H252-4FXM
Enterasys I3H252-8FXM
Enterasys I3H252-8TX-2FX
Enterasys I3H252-6TX-MEM
Enterasys I3H252-4FX-MEM
Enterasys I3H-12TX
Enterasys I3H-4FX-MM
Enterasys I3H-8FX-MM
Enterasys I3H-6TX-MEM
Enterasys I3H-4FXM-MEM
Enterasys I3H-MEM
Enterasys I3H-PWR
Enterasys I-MGBIC-GZX
Enterasys I-MGBIC-GSX
Enterasys 13H-DIN-KIT
Enterasys I3H-RACK-MNT
Enterasys K系列:
Enterasys K6-Chassis
Enterasys K6-FAN
Enterasys K6-MID-KIT
Enterasys K10-Chassis
Enterasys K10-FAN
Enterasys K10-MID-KIT
Enterasys K-AC-PS-1400W
Enterasys K-POE-4BAY
Enterasys K-POE-4BAY-RAIL
Enterasys KK2008-0204-F2
Enterasys KK2008-0204-F1
Enterasys KT2006-0224
Enterasys KG2001-0224
Enterasys KK2008-0204
Enterasys K-EOS-L3
Enterasys K-EOS-PPC
Enterasys S系列:
Enterasys S8-Chassis
Enterasys S8-Chassis-POE4
Enterasys S8-Chassis-POE8
Enterasys S4-Chassis
Enterasys S4-Chassis-POE4
Enterasys S3-Chassis
Enterasys S3-Chassis-POE4
Enterasys S-AC-PS
Enterasys S-POE-PS
Enterasys S-AC
Enterasys ST4006-0272
Enterasys ST4106-0248
Enterasys SG4101-0248
Enterasys ST4106-0348-F6
Enterasys ST1206-0848-F6
Enterasys SG1201-0848-F6
Enterasys SK1208-0808-F6
Enterasys ST1206-0848
Enterasys SG1201-0848
Enterasys SK1008-0816
Enterasys SOK1208-0102
Enterasys SOK1208-0104
Enterasys SOK1208-0204
Enterasys SOG1201-0112
Enterasys SOT1206-0112
Enterasys SSA-T4068-0252
Enterasys SSA-T1068-0652
Enterasys SSA-G1018-0652
Enterasys SSA-AC-PS-600W
Enterasys SSA-AC-PS-1000W
Enterasys SSA-FAN-KIT
The General Purpose Interface Bus (GPIB) makes the interconnection of automatic test instruments have a unified standard, which greatly promotes the development of automatic test technology. The GPIB bus has the characteristics of fast parallel bus transmission speed, high effective data rate, strong driving ability, communication distance up to 20m, good anti-jamming ability and generality, up to 15 devices can be connected on the bus and the transmission speed can reach 8Mbit / s, so the GPIB controller Ip core is designed with the modularization idea, the main modules include state machine module, Data Path module and decoding circuit module. The design of the state machine module includes 8 small modules (such as source hook and receiver Hook) , each small module is programmed with VHDL language, at last, the top-level module of the state machine is designed by invoking each sub-module and schematic diagram, and is analyzed and simulated in Synplify and Quartus II. In the same way, the design of Data Path is carried out by designing each sub-module first, and then the whole design. Finally, the State Machine top-level module, Data Path top-level module and multi-line message decoding circuit module are used to design the top-level IP core of GPIB controller. After the whole IPCore design is completed, the Core is downloaded to the selected DE2 special development kit CPLD chip by JTAG download method to verify the communication settings, and then the hardware is built after the success, so as to get the real GPIB controller. GPIB bus is a 24-core parallel passive bus, which consists of 8 ground wires and 16 signal wires. The 16 signal lines are 8 data lines (DIO1 ~ DIO8) , 3 handshake lines (Dav, NRFD, NDAC) and 5 management lines (ATN, Ren, IFC, EOI, SRQ) . The data transmission adopts the two-way asynchronous transmission mode of bit parallel and byte serial. Note that GPIB uses negative logic, i. e. low level (not more than 0.8 v) is logic 1, high level (not less than 2.0 v) is logic 0[2] . The basic principle of the GPIB bus is to use the controller as the server, to control the instruments by programming and using the GPIB bus, at the same time, the instruments also use the GPIB control chip to realize the data transmission with the server, its output signal to GPIB bus accords with IEEE488 standard, thus achieves the goal of automatic control and test. The system volume is only 7070mm, power consumption is less than 5W, median filtering rate is 20F / S, JPEG compression rate is above 25F / S. It not only meets the real-time requirement of the video processing system, but also has small volume and low power consumption. Moreover, the system has good flexibility and expansibility based on FPGA.
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