IC670CHS101
IC670CHS101
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IC697ACC621
IC697ACC624
IC697ACC644
IC697ACC700
IC697ACC701
IC697ACC702
IC697ACC715
IC697ACC720
IC697ACC721
IC697ACC722
IC697ACC723
IC697ACC724
IC697ACC726
IC697ACC727
IC697ACC728
IC697ACC729
IC697ACC730
IC697ACC732
IC697ACC735
IC697ACC744
IC697ACC800
IC697ACC801
IC697ACC802
IC697ACC803
IC697ACC804
IC697ACC805
IC697ACC806
IC697ACC820
IC697ACC821
IC697ACC822
IC697ACC900
IC697ADC701
IC697ADC701RR
IC697ADS701
IC697ALG230
IC697ALG230RR
IC697ALG320
IC697ALG320RR
IC697ALG440
IC697ALG440RR
IC697ALG441
IC697ALG441RR
IC697BEM711
IC697BEM711RR
IC697BEM713
IC697BEM713RR
IC697BEM715RR
IC697BEM721
IC697BEM721RR
IC697BEM731
IC697BEM731RR
IC697BEM733
IC697BEM733RR
IC697BEM741
IC697BEM741RR
IC697BEM761
IC697BEM761RR
IC697BEM763RR
IC697BEM764RR
IC697CBL700
IC697CBL709
IC697CBL803
IC697CBL811
IC697CBL826
IC697CGR772
IC697CGR935
IC697CGR935RR
IC697CHS750
IC697CHS750RR
IC697CHS770
IC697CHS771
IC697CHS782
IC697CHS782RR
IC697CHS783
IC697CHS783RR
IC697CHS790
IC697CHS790RR
IC697CHS790xSV
IC697CHS791
IC697CHS791RR
IC697CMM711
IC697CMM711RR
IC697CMM712
IC697CMM712RR
IC697CMM721
IC697CMM721RR
IC697CMM731RR
IC697CMM741
IC697CMM741RR
IC697CMM742
IC697CMM742RR
IC697CMM798RR
IC697CMM799RR
IC697CPM790
IC697CPM790RR
IC697CPM914RR
IC697CPM915RR
IC697CPM924RR
IC697CPM925RR
IC697CPU731
IC697CPU731RR
IC697CPU732RR
IC697CPU771RR
IC697CPU772RR
IC697CPU780
The system adopts the scheme of video processing based on FPGA and DSP to realize the whole process of video acquisition, processing and transmission. In real-time video image processing, the low-level preprocessing algorithm has a large amount of data and requires high processing speed, but the algorithm is relatively simple and suitable for hardware implementation with FPGA. The high-level Processing Algorithm has complex structure, and is suitable for the DSP chip with high operation speed, flexible addressing mode and strong communication mechanism. The most important characteristic of DSP + FPGA architecture is its flexible structure, strong commonality, suitable for Modular design, which can improve the algorithm efficiency, and its development cycle is short, and the system is easy to maintain and upgrade, suitable for real-time video image processing. The whole system is divided into three parts: video acquisition unit, video processing unit and video transmission unit. FPGA is used as the core control unit to filter the video signal, and DSP is used as the core processing unit to compress the JPEG of the video image A USB bus based on PDIUSBD12 is designed in the video transmission unit, which is responsible for the transmission of video signal. Hardware architecture, a complete video processing system, mainly by the video acquisition unit, video processing unit and video transmission unit composed of three parts. The system shall be designed in such a way as to ensure the seamless connection of all parts. The image acquisition unit is composed of FPGA and MB86S02 video acquisition chip, including video signal acquisition and pre-processing, converting the input video signal into digital image data which can be processed by the system, and stored in a certain format in a certain storage area. Image Processing Unit is the core of the system, image data compression processing, to achieve the system to achieve the function. The image transmission unit uses FPGA + USB to realize the video data transmission, and sends the compressed video image information to the receiving end through the USB bus based on PDIUSBD12 chip, at the receiving end, the image is uncompressed and displayed using an application written on a PC. The whole hardware system is composed of FPGA and DSP. FPGA is the video acquisition unit, and the video signal is preprocessed and sent to DSP. DSP is the core of the system, after the video image preprocessed by FPGA is compressed by JPEG, the performance of the DSP unit determines the performance of the whole system. After completing the image processing task, the DSP will return the result to FPGA, the compressed image information is written into the data buffer of the interface control chip by FPGA, and the interface control chip is responsible for the information transmission,
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